MTCA.4 at a Glance

 

MicroTCA is a trademark of PICMG http://www.picmg.org

The information on this page is tentative!

MTCA.4 specifies extensions to the MicroTCA standard to provide support for I/O bound applications in industry and science. The two key elements are Rear Transition Modules (µRTM) and timing and synchronization support.  

Clock and data distribution in a MTCA.4 crate:

The figure shows the distribution of clocks and triggers within a shelf. Some high-speed ADC’s require precise clocks: radial clock lines switch in the MCH are provided for these applications. Less demanding clocks and triggers are distributed via the eight bussed M-LVDS lines. Clock frequencies around 100 MHz are foreseen on the 100 # impedance matched bus. Triggers can be used to arm data recording of the ADC’s or to trigger readout processes in CPU’s. Figure 6-6 is an example of a fast digitizer with a FPGA controlling the processing of data. A radial distributed clock is used for the ADC’s. Data acquisition is triggered from the M-LVDS bus. And the board is able to compare ADC readings with a threshold to generate interlock signals. Those are distributed within the shelf on the bussed lines.

 

PCIe accomplishes data transfer between the ADC, FPGA and the CPU. The μTCA system provides more then 400 MB/sec transfer speed over 4 lanes available in each AMC. Further lines of ports 12 to 15 of the backplane (see Figure 6-4) can be used to combine ADC data of several boards via Giga-bit links of the controlling FPGA’s. An example from accelerators is the calculation of a vector sum of 32 cavities. Four ADC AMC’s are collecting the data; a fifth AMC implements a feedback controller. Such a complex system does not need external clock trigger or fast link lines since the backplane can distribute the required signals.

Sufficient space for connectors is a further requirement for front-end electronics. And ADC’s often need complex signal conditioning. Double size AMC’s and the same PCB size on the μRTM provide enough space for digital and analog electronics. Sensitive analog parts of the signal chain needs to be well separated and shielded from power converters and noisy digital lines. The layout of the AMC-μRTM connections is designed to support critical analog designs.

 

     

The foto shows a first full MTCA.4 complient implementation of a 12-slot shelf. It allows up to 4 power supplies and up to two MCHes. Cooling is from front to rear by two redundant fan units. Front AMC's and rear RTM's are controlled by separate fans. All slots are double midsize size. Single midsize size modules can be inserted as well.

MTCA.4 specifies a "common implementation" to reduce the number of possible variants and to increase the interoperability. Nevertheless, application specific implementations are possible, e.g. special backplanes, non-redundant versions, different number of slots or horizontal orientation of the AMC's. Important is the interoperability of modules (AMC and RTM).

© http://www.schroff.de

 

12 slot backplane:

Ports 0 to 11 are according to ScopeAlliance specifications.

Ports 12 to 15 are point-to-point, bi-directional links. This area can be application specific.

Ports 17 to 20 are 8 bussed lines, terminated with 100 Ohm on both sides, M-LVDS.

The second MCH is optional.

TCKLA and TCLKB are high precision clocksused by the application.

FCLKA is used for PCIe communication.

 

This is an example of a MTCA.4 shelf with 6 slots. It is a silent design for a developers desk. Airflow is from front to rear with separat fans. Power supply and fans are not redundant.

© http://www.elma.com

 

6 slot backplane:

Ports 0 to 11 are according to ScopeAlliance specifications.

Ports 12 to 15 are point-to-point, bi-directional links. This area can be application specific.

Ports 17 to 20 are 8 bussed lines, terminated with 100 Ohm on both sides, M-LVDS.

TCKLA and TCLKB are high precision clocksused by the application.

FCLKA is used for PCIe communication.

 

The equal space on the AMC and μRTM allows flexible combinations to design modular systems. An AMC with a FPGA requires many PCB layers and high-speed strip-line designs. This is time consuming development. It is an advantage to use these complex boards in multiple applications by providing μRTM’s as the adapter. μRTM’s can be implemented with 4 to 6 layers and more designers are able to do this. In other applications an expert RF designer is required to create high frequency RF front-end. The front and rear division of the task is convenient since one can partition the tasks to different skilled designers.

The MTCA.4 standard defines two 30pair ZD connectors. They fit on double mid-size AMC's. These connectors are available in 20 and 40pair versions and fit with the MTCA.4 specs. The 40pair version requires a double full-size AMC.

Maximum payload power (12V) consumption of a combined AMC and RTM module is 80W. The max. current of a rear module is 3A.

 

AMC modules are equipped with a Module Management Controller. MTCA.4 specifies the management implementation of the RTM. It is based on a EEPROM with the required module specification to detect valid RTMs that a compatible to the AMC. Only in case of a compliant board the 12 Volt payload power is switched on. The RTM may have an optional temperature sensor or ADC to measure the voltages. An I/O extender is controlling the LED's and the hot-swap handle.

The management of RTM's require a compatible MCH that supports additional MTCA.4 commands and event handling: the blue (hot swap) LED and the RTM handle state status. All other functions are implemented in the MMC of the AMC. E.g. the MMC calculates the total amount of 12 Volt power required by the AMC and RTM.

A MTCA.4 compatible MCH has to implement a separate fan control for the front and rear cooling. A second or redundant fan unit for front and rear is optional.

 

MTCA.4 defines ports 17 to 20 as 8 M-LVDS bus lines to distribute triggers, low precision clocks and interlocks. These lines can be driven and received by all AMC's in a shelf. Multi source interlocks can be implemented by holding the M-LVDS transmitter input high and driving the enable to low in case of an interlock condition. The receiver should be of M-LVDS type 2 (receiver is in a defined state with no source driving the line). A possible M-LVDS transceiver chip is DS91M040.

The MicroTCA specification defines records to describe the port connectivity. MTCA.4 adds record definitions for the M-LVDS bus.